The effective channel length (L.sub.eff) of a transistor is a critical device parameter as the drain current depends very sensitively on it. The conventional method of controlling the effective channel length is performed during the manufacturing of the semiconductor device by controlling the printed gate width. This is a very complicated process in which photolithography is employed to transform complex circuit diagrams into patterns which are defined on the semiconductor wafer in a succession of exposure and processing steps to form a number of superimposed layers of insulator, conductor and semiconductor materials. In photolithography, a light source is used to flood a photomask with light. The photomask carries the mask pattern of the circuit to be patterned on the semiconductor wafer. The flooding of the photomask with light causes the mask pattern to be transferred to a layer of photoresist that has been deposited on the semiconductor wafer. The photoresist is developed and unreacted areas are developed away, leaving the desired pattern and circuit features in the photoresist layer.
Following photolithography, appropriate processing steps, including etching, are then performed to produce the desired circuit structure. Etching, for example, involves the selective removal of material, either locally where windows are defined, or over the entire wafer without patterning. The etching process can be a complex process within the overall semiconductor manufacturing process, involving masking, precise control of etch times, etch chemistries, etc. in order to precisely form desired features.
One of the circuit features that must be well controlled is the physical gate length. As stated earlier, this is a very complicated process, requiring precise process control. Numerous effects from a number of process steps influence the actual physical gate length (i.e., the width of the gate produced by the photolithographic process). These steps include the preparation of the mask, lithography, and etching, any and all of which can cause unwanted variation in the physical gate lengths. Further, different process steps may have different impacts on different gate widths.
One of the advantages achieved by reducing the gate length is the increase in circuit speed. Traditionally, the focus of research to achieve submicron feature sizes has been in the lithography and etching areas. However, improvements in reducing the feature size are difficult to achieve in these areas, as it involves increased manufacturing costs and improved process control.